| L1 | Introduction. Intrinsic Semiconductors, Bond Structure, Holes and Electrons; ni(T). Dopants - Donors and Acceptors. no and po in Extrinsic (Doped). Sic: Thermal Equilibrium, Detailed Balance, nopo Product; no, po Given NA, ND. | Chap. 1 (all)
Chap. 2 (all) |
| L2 | Uniform Excitations: Uniform Electric Field and Drift (Review from Rec. 2). Uniform Optical Injection. Low Level Injection. Minority Carrier Lifetimes. Homogeneous Solution. | Chap. 3 (all except 3.3.2)
App. B |
| L3 | Non-uniform Injection and/or Doping. Diffusion. Continuity/Conservation. The Five Basic Equations. | Chap. 4 (all) |
| L4 | Linearization and Decoupling of 5 Basic Equations in Flow Problem Regime: Quasineutrality, Debye Length, LDx, and Dielectric Relaxation Time, τD; Minority Carrier Flow by Diffusion. Diffusion Equation(s) for n': General Solutions; Boundary Conditions; Procedure to find n, p, Je, Jh, Ex having n'. | Chap. 5 (all) |
| L5 | Non-uniformly Doped Material in Thermal Equilibrium. Electrostatic Potential (Using Einstein Relation); Poisson equation. no(x), po(x), Φ(x) when Doping Varies Slowly; Quasi-neutral Approximation; Extrinsic Debye Length, LDx. Begin Abrupt p-n Junction. | Chap. 6 (all) |
| L6 | Abrupt p-n Junction in Thermal Equilibrium; the Depletion Approximation. Expressions for W, xn, xp, Epk, Φb. Extension of Model to Biased Junctions: Argue can Replace Φb by (Φb - vA) if Charge Due to Currents Can be Neglected and All vA Appears across Junction. | Chap. 7 (7.1, 7.2) |
| L7 | Forward Biased Abrupt p-n Junction. Carrier Equilibrium with/across Space Charge Layer; Current Flow. Derivation of I-V Expression. Plots of Carrier Populatioins through Forward and Reverse Biased Short Base p-n Diodes (Emphasize Injection is into Lightly Doped Side). | Chap. 7 (7.3, 7.4.1a) |
| L8 | Review Diodes Current, and QN Region Excess Charge Stores and Diffusion Capacitance; Introduce BJT Structure, and Bipolar Junction Transistor (BJT) Operating Principles; Derive Currents for npn BJT in Forward Active Region; Introduce Base and Emitter Defects. | Chap. 7 (7.5 to end) |
| L9 | Superposition, Ebers-Moll Model for npn. Expressions for α and β. Large Signal BJT Characteristics and Models: Regions of Operation; Approximate Model Valid in Forward Active Region. β-model. Discussion of Limitations of Model and Extremes of Operation; Non-ideal Elements. | Chap. 8 (8.1) |
| L10 | Other Junction Devices (a Disguised Quiz Review): LEDs, Illuminated p-n Diodes; Superposition Solar Cells and Photodiodes. | Chap. 8 (8.2.1a) |
| L11 | MOS Structures. Discussion of Accumulation, Depletion, Inversion. Application of Depletion Approximation to MOS Capacitor to Relate Channel Charges to Gate Voltage. Flat Band Voltage; Threshold Voltage. | Chap. 9 (all except 9.5) |
| L12 | Gradual Channel Approximation for MOSFET i-v Characteristics; Quadratic Approx. Discussion of Pinch-off. Regions of Operation. | Chap. 10 (10.1.1a) |
| L13 | Summary of Static Large Signal BJT and MOSFET Models. Enhancements: Base Width/Channel Length Modulation (Early Effects); Charge Stores (diffusion and Depletion Stores in BJTs and MOSFETs). | Chap. 7 (7.2.2, 7.3.4)
Chap. 8 (8.2.1)
Chap. 10 (10.2.1) |
| L14 | Incremental Models for BJT (Hybrid-π) and MOSFET. npn vs. pnp; n-channel vs. p-channel; go, Early Voltage; Capacitances. Importance of Stable Bias Point. | Chap. 7 (7.4.2)
Chap. 8 (8.2.2, 8.2.3)
Chap. 10 (10.2.2, 10.2.3) |
| L15 | Basic Inverters as Building Blocks for Digital Logic, Memory; Performance Critieria. Begin MOS Logic; Inverter Options; Why CMOS. | Chap. 15 (15.1, 15.2) |
| L16 | CMOS in All its Glory: Comparison of Various Loads in Logic Context - Logic Swing, Speed, Power, Manufacturablity. Memory Cells. | Chap. 15 (15.2.4) |
| L17 | Begin Transistor Amplifiers; Common-source as Example. Performance Metrics: Voltage, Current, and Power Gains; Input and Output Resistances. Concept of Mid-band Frequency Range. | Chap. 11 (11.1, 11.2) |
| L18 | Basic Single Transistor Amplifier Stages. Common-base/-Gate and Emitter-/Source-Follower Amplifier Stages. Degenerate-Emitter/-Source Stages; Analysis and Features. Two-port Models. | Chap. 11 (11.3 to end) |
| L19 | Differential Amplifiers: Large Signal Analysis and Transfer Characteristics; Incremental Analysis and Half-circuit Analysis Techniques. | Chap. 12 (12.1, 12.2) |
| L20 | Complete General Differential Amplifiers. Current-source Biasing Circuits. Achieving Maximum Gain while Staying in Forward Active Region: Resistor Loads, Non-linear Loads. | Chap. 12 (12.3 to end)
Chap. 13 (13.1) |
| L21 | Active Loads: Lee Load; Current Mirror Loads; Double- to Single-ended Output Conversion. Multi-stage Amplifiers; Issues of Bias, Loading, Stage Choice. Applications and Advantages of CMOS. | Chap. 12 (12.4) |
| L22 | Bounding Mid-band; Methods of Open- and of Short-circuit Time Constants in High Frequency Analysis of Multi-stage Amplifiers. High Frequency Gain of Common-emitter/-Source Stage; Miller Capacitance. | Chap. 14 (14.1, 14.2) |
| L23 | A Look at the a Commercial Op-amp Design (741); Use to Discuss Some Special Stages (Darlington, Cascode, Push-Pull, etc.) Use of Capacitor to Stabilize Circuit. Expand upon Cascode as Important Multi-transistor Stage: Large Output Resistance, Excellent High Frequency Performance. | Chap. 13 (13.2 to end) |
| L24 | Intrinsic Limits to High Frequency Performance of MOSFETs and BJTs: wα, wβ, wt. Limits of Quasi-static Approx. | Chap. 14 (14.3; You can skip the derivation of the Gate Capacitance Expressions and jump from Eq. 14.30b to the result, Eq. 14.48, and what follows) |
| L25 | CMOS Gate Delay and Power Estimates; Relation to Device Dimensions. Scaling Rules. Example of Scaling: 386/486/Pentium. | Chap. 16 (16.3.1, 16.3.3) |
| L26 | Overview of the IC Industry, Analog and Digital. Review of Course and Suggestions for Follow-on Subjects. | All sections not previously assigned [just kidding; no more reading assignments, however if you want something useful to read, check out Chap. 15 (15.3, 15.4) and Chap. 16 (16.1, 16.2.1a)] |
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